Boundary scan, or as it is also termed JTAG is a powerful test technology that can be used to test today's highly complex and compact printed circuit assemblies. Boundary scan provides a highly effective means of testing circuits where access is not possible or convenient using other test technologies. It is found that the access required for techniques such as In-Circuit Test and Functional ATE is often not sufficient to enable a satisfactory test of the whole circuit to be undertaken. However JTAG, boundary scan is able to provide a comprehensive test of many circuits provided that the circuit is designed to enable JTAG, boundary scan techniques to be used.
JTAG, boundary scan is defined under IEEE 1149.1 which describes a four wire serial interface (a fifth wire may be used but is optional) for testing printed circuit boards and integrated circuits where access is limited. It is widely used on VLSI chips such as microprocessors, DSP chips, FPGAs and the like. These integrated circuits have boundary scan shift registers incorporated along with a state machine that enable testing to be accomplished without the need to physically access every node on the board or device. In this way boundary scan is an ideal test technology for many of today's test scenarios.
When designing a circuit that can use JTAG, boundary scan test techniques, there are some items that are mandatory, while others make the testing more effective or easier to accommodate. However incorporating as many techniques as possible into the design will enable the best test to be undertaken, and the most problems found, either during the development phase of the product, or during production or field test.
Component selection for JTAG, boundary scan
In any design the choice of components can have a major impact on the overall concept for the item. This is true when considering using boundary scan / JTAG techniques for testing a printed circuit board. It is important that the components that are included in the circuit that will be tested using boundary scan are chosen to accommodate testing using this methodology.
- Choose boundary scan compliant devices One of the primary considerations when designing any circuit is to choose the major components what will be used. If boundary scan test is envisaged, it is necessary to ensure that the major components are IEEE 1149.1 compliant. Today, most VLSI integrated circuits are 1149.1 compliant, but some of the smaller chips may not be, or the inclusion of JTAG may be optional. Wherever there is an option, ensure that the version with boundary scan is included.
- Avoid components with dual function connections Wherever possible avoid the use of integrated circuits where dual functionality is assigned to the JTAG pins.
- Ensure all devices support the required IEEE 1149.1 instructions Even when boundary scan compatible devices have been chosen it is necessary to ensure that they support the required instruction sets. Typically it is necessary to ensure that SAMPLE / PRELOAD, EXTEST, and BYPASS, are all satisfactory. These are mandatory so any IEEE 1149.1 device should support them. However it is also wise to pick devices that support the HIGHZ and IDCODE instructions.
Circuit design for JTAG, boundary scan
Once the required components have been chosen, it is necessary to ensure that the design for the circuit enables easy testing, and maximum access when using boundary scan / JTAG. There are a number of techniques available to ensure that the maximum use can be made of IEEE 1149.1.
- Correct connection of JTAG signals In order to ensure the correct operation of the boundary scan test, it is necessary to connect the Test Access Port (TAP) signals (TCK, TMS and if present TRST) in parallel to all the IEEE 1149.1 compliant devices. The TDI and TDO are then used to form the serial daisy chain around the devices, allowing the serial data to pass from one chip to the next. Data is sent into the TDI of the first chip, and then TDO from the first chip is connected to TDI of the next and so forth. Finally the data is taken from the TDO of the last IC in the daisy chain.
- Partition circuit according to component manufacturers It is often necessary to separate out the FPGAs or cPLDs from different manufacturers because they use different configuration tools. In view of the different operation under some circumstances it is easier to partition the boundary scan chains so that the individual manufacturers tools can communicate with the relevant devices.
One important aspect associated with any form of electronics test, and this includes JTAG, boundary scan is that of test access. This is obviously important in terms of choosing components and designing the circuit correctly. However physical access is equally important. To ensure that circuits can be tested easily, many boards include a JTAG connector specifically for test. This JTAG connector can be a very low cost item as it only needs to be used during the production and test phases of the product. However good reliable test access is very important. The JTAG connector can save time, especially if it provides very reliable performance where other methods may not be so reliable. Poor reliability can lead to many house of lost time fault finding problems associated only with the test access. In view of this and the ease of performing tests, a JTAG connector can be a cost effective addition to a board in many cases. A JTAG connector should therefore be considered as one of the design considerations at the earliest part of the design phase of a product.
This is not an exhaustive summary of all the precautions to take when designing a circuit board that will use JTAG, boundary scan. However it gives a useful guide to some of the basics that may be employed.